Controller Clock Speed
Frequently specific times for delays between character data transfers or commands are given for these displays. There's a hidden assumption in these numbers: the internal clock speed at which the Hitachi 44780 controller is running. Usually the times that are commonly available assume a clock speed of somewhere around 250kHz. The actual clock speed of the controller can be as low as 140kHz. If you don't read the BUSY signal off of these displays (as in my circuit), you should provide delays that accomodate the slowest displays.
Surplus = Unknown
The best prices on these displays come from surplus houses. Part of the reason I used one of these LCD displays on this project was my principle of keeping parts count to a minimum. I have a wide range of displays on hand that are more in line with a retro design--hexadecimal displays with built in latches and decode logic, for example. But the LCD is low power, and provides many more digits of display than they do. The whole LCD was also many times cheaper than even one digit of the hex LED displays.
With surplus, you don't usually get specific details on the display. In this case it's safest to assume the lowest performance. This also allows later substitution of other LCDs without having to rewrite all the delays.
There are two normal command execution times. One long, one short:
Instruction Exec. Time at 140kHz, 250kHz Clear Display (01) 2.93mS 1.64mS Display Home (02, 03) 2.93mS 1.64mS Entry Mode Set (04-07) 2.93mS 1.64mS Display Control (08-0F) 71.4uS 40uS Cursor/Display Shift (10-1F) 71.4uS 40uS Function Set (20-3F) 71.4uS 40uS Set CGRAM Address (40-7F) 71.4uS 40uS Set DDRAM Address (80-FF) 71.4uS 40uS Data Transfer Times Data Write Time 71.4uS 40uS Data Read Time 71.4uS 40uS Busy Flag Read and Address 1.8uS 1uS
You can set up one delay for any command of 07 or lower, and another for any other command or data transfer.
LCDs and 8085 Timing
8085 instructions are timed in T-States. Each T-State is one 8085 clock cycle. The fastest instructions on the 8085 require 4 T-States to complete. They're internal-only instructions like NOP and register MOVs. Other instructions take longer.
If we write our code to allow the slowest LCD to work with the fastest 8085, we'll be safe no matter what changes we make to the system. This may be too long a delay with a slower system, however, so a compromise may be in order.
8085AH-1 T-State Time at 6MHz: 166.7nS 8085 T-State Time at 3.125MHz: 320nS
For the MAG-85, I use the slower speed. This system was not created to be a speed demon. So the delay times in my software will be safe for any oscillator frequency up to 6.25MHz. Lengthen delay times if you use a 5MHz or 6MHz 8085--see below.
8085 Delay Loop Times
I use the following delay loops as models for delay timing for the LCD (and for all delays in my system software):
DELAY: XRA A SDELAY: DCR A JNZ SDELAY RET FULLDELAY: XRA A MOV B, A LDELAY: DCR A JNZ LDELAY DCR B JNZ LDELAY RET
If my T-State counts are correct (I make no guarantees), a DELAY should last 3585 T-States, not counting CALL and RET times. A CALL to SDELAY should last 14 times the number in A at CALL minus 3 T-States [(A*14)-3 T-States], again not counting CALL and RET or set up times.
FULLDELAY lasts 920,325 T-States. LDELAY lasts (B*3591)-3 T-States, assuming A is 0 on entry.
Using these figures, we can calculate about how many loops we want for the appropriate delay times:
Clock Speed: 6MHz 3.125MHz DELAY: 597.5uS 1.147mS FULLDELAY: 136.7mS 294.5mS SDELAY: A*2.33uS-0.5uS A*4.48uS-0.96uS LDELAY:(A=0) ~B*599uS ~B*1.15mS CALL/RET(28T): 4.7uS 9uS
For the slow commands we should call LDELAY with B set to 3 to be belt-and-suspenders certain that we're giving the display enough time to respond at a low clock speed on a cold day while driving uphill through a thunderstorm. Not even counting the time for CALL and RET, this gives us just about 3.45mS of delay. Plenty of leeway over the 2.93mS we need.
For the other commands, we should preload A with a value of 0x10 or 16 to give the display time under worst circumstances. When we include the 9uS that the CALL and RET will add, not even counting the setup time for A, this will give us at least 79uS of delay, plenty over the 71.4uS required.
And if a read of BUSY is performed, our processor is slow enough that we need no delay.
Pulsing LCD Enable Line
We need to check timing for data set up times for the LCD, E strobe to clock the data in, and data hold times after the E strobe ends. The nominal times for the LCD (assuming 140kHz clock) are 250nS from RS, R/W valid until E is asserted; Assert E for 804nS; Data valid for 358nS before E falls; and Data valid for 36nS after E falls.
With the 8085 at any speed, meeting these constraints is easy if using the LCD on an OUT port. The minimum time between state changes is 17 states if OUT commands are mixed with accumulator immediate commands to manipulate bits in the output byte. E.g.:
(set data value in A, set RS bit) OUT 00 ; 10 T-States ORI $20 ; Set E bit, 7 T-States OUT 00 ; 10 more T-States ANI $DF ; Clear E, 7 States OUT 00 ; 10 States
This creates an E strobe that lasts 17 T-States, or 5.44uS at 3.125MHz. We can't possibly run fast enough to undercut the LCD's timing if we transfer the data this way.