Adding an Address Latch

8085 Circuit image showing latch IC

Catch the Address Before It's Gone.

The Address Latch is a small first step beyond the Free Run circuit. It prepares the 8085 for talking to a real memory chip.

Dividing Addresses from Data

The Latch

The IC we'll be using for a latch is a 74373. The specific version I use is a 74LS373, but a 74373 or 74HCT373 would work just as well. Our memory would work with a 74C373 or a 74HC737 as well, but depending on what gets added to the system later, it is probably best to stick with either the 74373, 74LS373, or 74HCT373. These versions will guarantee the output voltages we may need later.

The little IC you see on the right in the photo above, nearly hidden behind green and orange wires, is the latch. The orange wires carry the signals from 8085 AD0-7 to the latch. The green wires carry only the address signals out of the latch. This is thanks to the orange and white wire, which takes the ALE signal from the 8085 to the latch, so it "knows" when to latch the address signals.

There's one other control line on the latch, Output Enable. For our purposes we want the latch to turn on its outputs all the time, so we tie this line to ground.

Here's the wiring diagram for the latch:

latch chip wiring diagram

Testing the Latch

The latch's output can be checked thoroughly using an oscilloscope, but it can be checked sufficiently well for now with a logic probe as well. With an o-scope, check the relative timings of each of the A0-7 outputs. Each output should have half the rate of change of the next lower numbered address output.

With a logic probe, for now simply verify pulsing signals on each line. We'll be doing testing later with the memory added to make sure that the address lines are in the correct order (though it never hurts to check visually, now.) Attaching LEDs to the address lines on the latch won't do us any good. Those lines change state too rapidly for our eyes to see.

A Bus Divided

Now we have the address lines without any data on them. This means we can connect standard memories. We only need to latch the address lines. The data signals don't have to be latched, in fact the system wouldn't work correctly if we did latch them. Data outputs are controlled using the 8085's other control lines, so data will only appear on the AD0-7 lines when we want it to, when it won't interfere with addresses. So long as we build everything correctly.

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